1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
|
/*
* TOP2049 Open Source programming suite
*
* Microchip - version 01
* FPGA Main bottomhalf implementation
*
* Copyright (c) 2012 Pavel Stemberk <stemberk@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`include "common.vh"
`define DELAY42NSEC(D42NSEC) __delay_count <= (D42NSEC) - 1;//41.666 ns wait cycle if D42NSEC = 1
`define CMD_SENDINSTR 1
`define CMD_SENDDATA 2
`define CMD_READDATA 3
`define ALL_WITHOUT_ZIF(NAME_, ID_MAJOR_, ID_MINOR_) \
`BOTTOMHALF_BEGIN(NAME_, ID_MAJOR_, ID_MINOR_) \
/* Programmer context */ \
reg [7:0] prog_count; \
reg dut_sci_manual; \
reg dut_sci_auto; \
wire dut_sci; \
reg dut_sdio_driven; \
reg dut_sdio_value; \
reg dut_vpp; \
reg [15:0] sdi_buf; \
reg [15:0] sdo_buf; \
\
initial begin \
prog_count <= 0; \
dut_sci_manual <= 0; \
dut_sci_auto <= 0; \
dut_sdio_driven <= 0; \
dut_sdio_value <= 0; \
sdi_buf <= 0; \
sdo_buf <= 0; \
dut_vpp <= 0; \
end \
\
`ASYNCPROC_BEGIN \
if (`CMD_IS_RUNNING) begin \
case (`CMD_STATE) \
0: begin \
if (`CMD_IS(`CMD_SENDINSTR) || \
`CMD_IS(`CMD_SENDDATA)) begin \
dut_sdio_driven <= 1; \
end else begin \
dut_sdio_driven <= 0; \
end \
`CMD_STATE_SET(1) \
`DELAY42NSEC(5) \
end \
1: begin \
dut_sci_auto <= 1; /* CLK hi 80ns after this moment we need to be prepared in CMD_READDATA case */ \
case(`CMD_NR) \
`CMD_SENDDATA: begin \
dut_sdio_value <= sdi_buf[prog_count];\
end \
`CMD_SENDINSTR: begin \
dut_sdio_value <= sdi_buf[prog_count+1];\
end \
endcase \
`CMD_STATE_SET(2) \
`DELAY42NSEC(5) \
end \
2: begin \
if (`CMD_IS(`CMD_READDATA)) begin \
sdo_buf[prog_count] <= zif[`DUT_SDIO];\
end \
prog_count <= prog_count + 1; \
`CMD_STATE_SET(3) \
`DELAY42NSEC(5) \
end \
3: begin \
dut_sci_auto <= 0; /* CLK lo */ \
\
if ((prog_count == 6 && `CMD_IS(`CMD_SENDINSTR)) ||\
(prog_count == 16 && (`CMD_IS(`CMD_SENDDATA) ||\
`CMD_IS(`CMD_READDATA)))) begin\
`CMD_FINISH \
prog_count <= 0; \
if (`CMD_IS(`CMD_SENDINSTR) || \
`CMD_IS(`CMD_SENDDATA)) begin\
dut_sdio_driven <= 0; \
end \
end else begin \
if (`CMD_IS(`CMD_READDATA)) begin\
`DELAY42NSEC(40) \
end else begin \
`DELAY42NSEC(5) \
end \
`CMD_STATE_SET(0) \
end \
end \
endcase \
end \
`ASYNCPROC_END \
\
`DATAWRITE_BEGIN \
`ADDR(2): begin /* Run command */ \
`CMD_RUN(in_data) \
end \
`ADDR(3): begin /* Load SDI LO BYTE sequence */ \
sdi_buf[0] <= 0; \
sdi_buf[8:1] <= in_data; \
end \
`ADDR(4): begin /* Load SDI HI BYTE sequence */ \
sdi_buf[14:9] <= in_data[5:0]; \
sdi_buf[15] <= 0; \
end \
`ADDR(5): begin /* Set signals manually */ \
dut_sci_manual <= in_data[0]; /* SCI */ \
end \
`DATAWRITE_END \
\
`DATAREAD_BEGIN \
`ADDR(0): begin /* Get SDO sequence high (bits 8-13) */ \
out_data[5:0] <= sdo_buf[14:9]; \
out_data[7:6] <= 0; \
end \
`ADDR(2): begin /* Read status */ \
out_data[0] <= `CMD_IS_RUNNING; /* busy */ \
out_data[1] <= zif[`DUT_SDIO]; /* Raw SDO pin access */\
end \
`ADDR(3): begin /* Get SDO sequence low (bits 0-7) */ \
out_data[7:0] <= sdo_buf[8:1]; \
end \
`DATAREAD_END \
\
assign dut_sci = `CMD_IS_RUNNING ? dut_sci_auto : dut_sci_manual;
/* vim: filetype=verilog:shiftwidth=8:tabstop=8:softtabstop=8
*/
|
